1. Field of the Invention
The invention relates generally to computer automated design of integrated circuits and, more specifically, to hierarchical pushdown of cells and nets in logical depth.
2. Description of the Related Art
Conventional physical design techniques for integrated circuits employ a hierarchical representation of circuit elements, with top-level circuit structures constraining lower-level structures. For example, physical design of a top-level clock grid may constrain floor-planning and placement of low-level circuit elements coupled to the clock grid. Following conventional techniques, the top-level clock grid is first designed to completion and verified before physical design of low-level circuit elements coupled to the clock grid may be completed.
During the course of completing a final integrated circuit design, the clock grid may need to change, the low-level circuit elements may need to change, and/or the physical design of the low-level circuit elements may need to change. A change on any level may require a design effort at all levels of hierarchy to accommodate the change. Each design effort on each level of hierarchy typically requires a significant amount of time to complete. Because lower levels are conventionally constrained by and sequentially dependent on higher levels, design efforts associated with each level of hierarchy are serialized, leading to lengthy design cycles and inefficient use of design resources. Furthermore, the scope of design change that may be effected on a full-chip structure is highly constrained because such a change would require a major redesign at all levels of hierarchy.
As the foregoing illustrates, what is needed in the art is a technique that enables greater design efficiency in hierarchical integrated circuit designs.